Memory devices find ubiquitous use in computing devices. Dynamic random access memory (DRAM) is commonly used as working memory in computing devices. The working memory is often volatile (it loses state if power is interrupted to the system), and provides temporary storage for data and programs (code) to be accessed and executed by the system processor(s).
Memory device access for main system memory in a computing device does not traditionally include the use of cyclic redundancy checking (CRC). There is known use of CRC with graphics controllers; however, the use of CRC in graphics controllers is performed with a separate pin in the hardware devices. Use of a mode register allows the setting of a CRC mode, but is a process that involves several operations, which introduces a certain amount of overhead. The overhead may be considered acceptable for setting the CRC in an initialization routine. However, the overhead provides a delay that could be significant outside of an initialization or setup operation.
FIG. 1 is a timing diagram of prior art memory access error detection. As seen in diagram 100, back-to-back reads with CRC enabled are performed. Clock signal 110 provides a timing reference for the occurrence of the various activities. There are eighteen clock cycles shown, T0-T17. Command line 120 illustrates when read commands occur in the example. The discussion of diagram 100 is only made in reference to the read commands, thus, except for the read commands the rest of the command signal is filled with “Don't Care” hash marking.
Three back-to-back reads are shown, R0, R1, and R2. There is a delay of tCL between the issuance of the read command, and the start of the transfer of data (D) on data signal 130. For purposes of illustration, data transfers D0, D1, and D2 are blocked in dashed lines to show what part of data signal 130 corresponds with which command (R0, R1, and R2 respectively). Back-to-back reads to different bank groups are assumed to take 5 clocks or 5 clock cycles (tCCD_S=5). There are two data transfers (D) per clock. Each data transfer takes 10 UI (unit intervals, or 5 clocks, with 2 UIs per clock). It will be observed that the CRC signal occupies 2 UI for each data transfer.
The lack of CRC means that certain errors introduced into data access operations may negatively affect the data read. However, the use of CRC can have a negative impact on memory access performance.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein. An overview of embodiments of the invention is provided below, followed by a more detailed description with reference to the drawings.